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Author: Enrico Weigelt, metux IT consult
Date:  
To: dng
Subject: Re: [DNG] Purism Librem and disabling Intel ME: it can be done [ Re: TALOS 2 - The Libre Owner Controlled POWER9 Workstation/Server ]
On 07.09.2017 16:12, Erik Christiansen wrote:

> If the firewall is on a FPGA, then we know what every gate is doing, as
> we have the VHDL source for it.


An purely FPGA-based firewall (w/o an cpu in it), specifically
synthesized for a given ruleset seems an very interesting approach.

Anyone here w/ some practical vhdl experience ?


--mtx