On 07.09.17 17:34, Enrico Weigelt, metux IT consult wrote:
> On 07.09.2017 16:12, Erik Christiansen wrote:
>
> > If the firewall is on a FPGA, then we know what every gate is doing, as
> > we have the VHDL source for it.
>
> An purely FPGA-based firewall (w/o an cpu in it), specifically
> synthesized for a given ruleset seems an very interesting approach.

No, one of the variety of CPUs implemented on FPGAs, so not so curious
at all. Some FPGAs contain RAM areas, improving the gate efficiency of
e.g. a CPU implementation.

Erik