On Thu, 17 Aug 2017 at 16:34:30 -0700
Rick Moen <rick@???> wrote:

> Quoting Alessandro Selli (alessandroselli@???):
>
>>>> "This is a NOMMU chip, implemented as Harvard architecture (separate
>>>> Instruction and Data busses) with a 5 stage pipeline, with 16k cache
>>>> (8k instruction, 8k data), supported by a memory controller
>>>> interfacing with up to 256 megabytes of lpddr memory (in one low cost
>>>> memory chip)."
>>>>

>>>>   So, it's a 32-bit chip with no MMU, no FPU, 2-way SMP and 256 MiB
>>>> maximum memory.  :-(    

>>>
>>> When you say 'it', you refer to the SH2-compatible chip from 2015, which
>>> was merely the -start- of the Hitachi SuperH-revival project.
>>
>> No, 2-way SMP support was added in 2016. Looks like that was the last
>> release.
>
> But the text you quoted (above) described the 2015 SH2-compatible chip,
> exactly as I said, not the 2016 one. Thus my point.

Please, read it in full:

http://j-core.org/roadmap.html

    It was announced at Linuxcon Tokyo in 2015, with a second release at
    ELC 2016 adding 2-way SMP support.

> You described only the _start_ of the roadmap.

I described what is available *now*.

> You said nothing (until
> now) about even the 2016 immediate successor.

Again: described what is available *now*. I don't care what they plan to
produce in the future. I might take that in consideration when it's going to
materialize.

>>> Why did you ignore the rest of the roadmap?
>>
>> Because it's just a roadmap. I wrote about what is available now.
>
> What is available now is not all that interesting.

Which is exactly my point. No product? No market.


Bye,


Alessandro