On Thu, 17 Aug 2017 at 15:14:26 -0700
Rick Moen <rick@???> wrote:

> Quoting Alessandro Selli (alessandroselli@???):
>
>> Plus, it seems to target SoC and IoT devices rather than desktops:
>>
>> http://j-core.org/roadmap.html
>
> _Initially_, yes. But not thereafter.
>
>> "This is a NOMMU chip, implemented as Harvard architecture (separate
>> Instruction and Data busses) with a 5 stage pipeline, with 16k cache (8k
>> instruction, 8k data), supported by a memory controller interfacing with
>> up to 256 megabytes of lpddr memory (in one low cost memory chip)."
>>
>> So, it's a 32-bit chip with no MMU, no FPU, 2-way SMP and 256 MiB
>> maximum memory. :-(
>
> When you say 'it', you refer to the SH2-compatible chip from 2015, which
> was merely the -start- of the Hitachi SuperH-revival project.

No, 2-way SMP support was added in 2016. Looks like that was the last
release.

> Why did
> you ignore the rest of the roadmap?


Because it's just a roadmap. I wrote about what is available now.


Alessandro