Quoting Alessandro Selli (alessandroselli@???):

> Plus, it seems to target SoC and IoT devices rather than desktops:
>
> http://j-core.org/roadmap.html

_Initially_, yes. But not thereafter.

> "This is a NOMMU chip, implemented as Harvard architecture (separate
> Instruction and Data busses) with a 5 stage pipeline, with 16k cache (8k
> instruction, 8k data), supported by a memory controller interfacing with up
> to 256 megabytes of lpddr memory (in one low cost memory chip)."
>
> So, it's a 32-bit chip with no MMU, no FPU, 2-way SMP and 256 MiB maximum
> memory. :-(

When you say 'it', you refer to the SH2-compatible chip from 2015, which
was merely the -start- of the Hitachi SuperH-revival project. Why did
you ignore the rest of the roadmap?

By the time one gets to SH4-compatible (slated for next year, in the
roadmap), one has a very respectible 32-bit RISC CPU (with, of course,
MMU, FPU, etc.), and the next unit after that would (if this pans out)
be the first 64-bit ones.

J64: 2019-ish, new 64-bit mode

Instead of shmedia's Itanium-like approach, we plan a more x86-64
approach for j4, with 32 bit compatibility mode running stock sh4 code
(at least in userspace), and a mode bit that switches to 64 bit register
size and reinterprets a small subset of the existing instructions and
leaves the rest alone.

That is no longer a little bitty embedded SoC.