Edward Bartolo <edbarx@???> writes:
> Hi Rainer,
>
> Thanks for trying to help me.
>
> Rainer wrote:
> -------------------------------
> SRC := src
> TMP := tmp
> SRCS := auxiliaries.c signal_functions.c main_gui.c dialog_gui.c
> sn-lightweight.c
> OBJS := $(addprefix $(TMP)/, $(SRCS:.c=.o))
>

> sn-lightweight: $(OBJS)
>         $(CC) $(GTK2FLAGS) -o $@ $^

>

> $(TMP)/%.o: $(SRC)/%.c
>         $(CC) $(CFLAGS) -o $@ $<
> ----------------------------

>
>
> SRC, TMP and SRCS are macros. The ':=' to me seems equivalent to '='
> and in the code snippet you sent me is used as an assignment operator
> like '='.

As I already wrote: := means 'expand the right-hand side once and
assign the result to the macro on the left-hand side'. In contrast to
this, = records the text on the right which is expanded whenever the
macro name on the left is being used. This implies the expanded value
will change in case the values of macros contained in the recorded
string change.

Simple example:

------
CMD = echo $@

b:
    $(CMD)

c:
    $(CMD)
------

Saving this as Makefile in some directory and then running 'make b' or
'make c' will execute 'echo b' or 'echo c' ($@ is a macro representing
the current make target. When changing the = to :=, the command will
always be just echo as $@ isn't set at the point where the CMD macro is
defined.


> ':.c=.o' is telling the interpreting program to iteratively assign the
> .c file to $@ and a .o file with the same name to $^.

No. That's a suffix substition.

$(SRCS:.c=.o)

will expand to the value of SRCS will each .c replaced by a .o.

>> OBJS := $(addprefix $(TMP)/, $(SRCS:.c=.o))
> addprefix $(TMP) is used to iteratively to prepend 'tmp/' to every
> file listed in SRCS.
>
>

>> sn-lightweight: $(OBJS)
>>        $(CC) $(GTK2FLAGS) -o $@ $^
> This is telling gcc to take the .o file and link them into an
> executable with the name sn-lightweight. The $^ stands for files taken
> from OBJS and the $@ stands for sn-lightweight, the target.

>

>> $(TMP)/%.o: $(SRC)/%.c
>>        $(CC) $(CFLAGS) -o $@ $<
> This time the % is telling gcc to iteratively create a .o file in tmp
> taking the source file with the same name from src/.

>

> I think, gcc should take -c to create .o files instead of a complete
> executable as you noted in your last email. -c should go in:
>> $(TMP)/%.o: $(SRC)/%.c
>>        $(CC) $(CFLAGS) -c $@ $<

One other noteworthy thing here: $^ expands to all declared
dependencies, $< just to the first one. The latter is useful because it
enables declaring depedencies which won't be passed to the command, eg,
C header files.