Edward Bartolo <edbarx@???> writes:
> Here is my Makefile for sn-lightweight (simple-netaid-lightweight):
> ----------------------------------------------------------------------------
> CC=gcc
> SRCPATH=./src
> CFLAGS=-Iinclude
> GTK2FLAGS=`pkg-config --libs --cflags gtk+-2.0`
> D=src/
> SOURCEFILES=$(D)auxiliaries.c $(D)signal_functions.c $(D)main_gui.c
> $(D)dialog_gui.c $(D)sn-lightweight.c
>
> all: clean sn-lightweight
>

> sn-lightweight:
>     $(CC) $(CFLAGS) $(GTK2FLAGS) -o sn-lightweight $(SOURCEFILES)

>

> clean:
>     rm -f sn-lightweight
> --------------------------------------------------------------------

>
> Althought make -f Makefile succeeds to compile and build an executable
> and calling "git buildpackage --git-ignore-new" work, I think this
> file can be improved. For instance, I find it rather ridiculous of
> having to use $(D) repeatedly for every .c source file.

I'm assuming that you don't mind using GNU make features.

You could use

SOURCEFILES=$(addprefix $(D), auxiliaries.c signal_functions.c main_gui.c dialog_gui.c sn-lightweight.c)

But that's still not a terribly good idea because declaring that the
executable depends on the source files implies they'll all be recompiled
for every change to one of them. One would usually have the executable
depend on the object files and use 'generic rules' to turn source files
into objects files and objects files into an executable, eg (that's how
I'd do that, untested example, using a directory tmp for generated files

------
SRC := src
TMP := tmp
SRCS := auxiliaries.c signal_functions.c main_gui.c dialog_gui.c sn-lightweight.c
OBJS := $(addprefix $(TMP)/, $(SRCS:.c=.o))

sn-lightweight: $(OBJS)
    $(CC) $(GTK2FLAGS) -o $@ $^

$(TMP)/%.o: $(SRC)/%.c
    $(CC) $(CFLAGS) -o $@ $<
-------

The := means 'expand once upon encountering it'. This is still fairly
unsophisticated.